Highspeed 64kb SRAM. Goal is to optimize metric
Architecture:
-        Increased VDD to 2.5V – WHY?

-        Picked block size from prior year’s group’s analysis

Block diagram
-        I liked the walk through of operation on the block diagram; some highlights on the slide might help with this

Circuits
-        Used TX gates a lot of places

-        6T bitcell; aware of some other options, but went traditional route.

-        Sizing: looked at ratios using reference equations; optimized in mathematica

o   Compared to prior years as well. Picked up some test methods.

o   Seemed to be based primarily on research of other people’s choices, although verified

o   Would be nice to see some of the plots to show quantifiable justification for your choice

-        Latching voltage SA selected

o   You mentioned a few pros and cons of different options and research – that’s good.

o   Did you do any simulations to compare them? Would be nice to see quantifiable justification

-        Layout (removed taps for presentation)

o   Showing layout from Cadence is ok sometimes, but it’s really hard to see. Better to redraw or annotate the cadence version

o   Tiled cells look like they have large gaps in between. Why couldn’t the cells abut directly and share diffusion?

o   Have a block layout with peripherals – this layout from Cadence is more acceptable bc you annotated it and used it chiefly to illustrate that it was complete.

o   6 TX gates in series – presumably with no buffers. Any repercussions?

-        Simulations

o   1b array model

§  32b word sims were requested

o   What parasitics did you include? RC?

o   Very limited simulation results; inconclusive about whether the memory actually works

-        Metrics

o   Estimates – not high confidence in them; still working on improvements before paper

o   0.54ns read time

o   0.11ns write time

-        Future

o   Block level partitioning didn’t work as well

o   Would like to move on the Pareto curve

o   Like to use SKILL

o   Add ECC

o   Vectorize signals for testing

Metrics:
 
PRESENTATION
Well practiced. Ties!! Nice looking slides. Good qualifications and appropriate level of detail. Good explanations. Everyone participated.
Cited sources.
QUESTIONS
Q. Why did you choose 2.5V?
A. Speed, more reliable write
Q. What is fastest speed?
A. 0.54ns going through the entire array
Q. Design layout improvements? Is the layout a big impact?
A. Layout has an impact, but don’t a feel for the relative impact vs circuits.
Q. How is the total metric so much better when the submetrics are similar?
Q.
 
 
Q. What was key lesson? What did you learn?
A. Clear division of labor. Project planning.  Really conservative with timeline. SKILL and ocean next time.